HISTORY
Those who worked in the semiconductor industry in the 80's may remember that almost all (over 70%) semiconductor startups funded by venture capital were successful. Design complexity was 50-100,000 transistors designed by hand. Logic Synthesis/Abstract Hardware Description Languages /Complex Mixed Signal Design....did not exist. Design Verification consisted of manually tracing lines with colored pencils. Software /Firmware were largely non existent except on simple 4-8 bit microprocessors.
Success was more easily predictable as were estimations of costs/time to execute. The situation started to change by the late 80's with complexity roughly doubling each year. Abstract high level hardware description languages like VHDL and RTL were born.
In 1990 Synopsys was born inventing logic synthesis, allowing logic design to be designed 100 times faster! Standard Cell Libraries and Place & Route technologies were born. With CMP(Chemical Mechanical Polishing of silicon)invented by IBM ,multilevel metal layers and multimillion gate chips put an end to manual design verification. Complex random assertion based design verification was born..100% test bench coverage required skilled expertise in a discipline which did not exist .Hardware /Software Co-Design was born. Mixed Signal design was born. Systems-on-Chip became the buzz word.
Design costs /time for complex chips exploded to over Euro 20M per design..(now easily doubled to Euro 40-50M!) 50-80 people team sizes became the norm for a single project chip design project. For each design engineer, 2 verification engineers became the norm to guarantee design success. Today if 70% of the design team and effort is not verification (a discipline and skill set in itself) the chip does not work the first time (85% mortality rate of all design starts industry wide today) Pioneered by ST and Texas Instruments in the early 90's and followed by 70% of the semiconductor industry worldwide (starting year 2000) ,massive India based chip design centers were born to make the cost/availability of large technical teams affordable and even possible given the sharp drop in electrical engineering graduates in USA,EU and Japan.
The Startups did not consider or were not able to avail the low cost design center possibility due to lack of management and multicultural global operating skill sets and the natural NIH /resistance of engineering managers.. Typically the founders of technical start-ups.
Semiconductor Start-up Failure Rate Explosion..95% over past 20 years Venture Capitalists have funded on the average 140 semiconductor startups per year since 1990..ie 20 years(source :FSA ).On the average each startup has taken in between 35M$(low case)-90M$(High case)..and in some cases over 220M$( Icera Ltd..Bristol). Success rate has dropped to below 5%!
The most common denominator for lack of a successful result ,apart from product strategy/market errors, is a gross underestimation of costs/time to execute today's chip complexity, requiring far greater yet highly skilled microelectronics resources in both design and software and even more often in Design Verification and Validation .Typically entrepreneurial startup teams do not have the management /global operating skill sets to solve this problem by creation of a low cost design center offshore as most large multinationals and savvy US companies have done. As stated earlier the matter is often compounded by typical engineering management NIH and a strong resistance to work with remote design centers by engineers who have never worked with foreigners and who naturally prefer to have all team members on location.
Success was more easily predictable as were estimations of costs/time to execute. The situation started to change by the late 80's with complexity roughly doubling each year. Abstract high level hardware description languages like VHDL and RTL were born.
In 1990 Synopsys was born inventing logic synthesis, allowing logic design to be designed 100 times faster! Standard Cell Libraries and Place & Route technologies were born. With CMP(Chemical Mechanical Polishing of silicon)invented by IBM ,multilevel metal layers and multimillion gate chips put an end to manual design verification. Complex random assertion based design verification was born..100% test bench coverage required skilled expertise in a discipline which did not exist .Hardware /Software Co-Design was born. Mixed Signal design was born. Systems-on-Chip became the buzz word.
Design costs /time for complex chips exploded to over Euro 20M per design..(now easily doubled to Euro 40-50M!) 50-80 people team sizes became the norm for a single project chip design project. For each design engineer, 2 verification engineers became the norm to guarantee design success. Today if 70% of the design team and effort is not verification (a discipline and skill set in itself) the chip does not work the first time (85% mortality rate of all design starts industry wide today) Pioneered by ST and Texas Instruments in the early 90's and followed by 70% of the semiconductor industry worldwide (starting year 2000) ,massive India based chip design centers were born to make the cost/availability of large technical teams affordable and even possible given the sharp drop in electrical engineering graduates in USA,EU and Japan.
The Startups did not consider or were not able to avail the low cost design center possibility due to lack of management and multicultural global operating skill sets and the natural NIH /resistance of engineering managers.. Typically the founders of technical start-ups.
Semiconductor Start-up Failure Rate Explosion..95% over past 20 years Venture Capitalists have funded on the average 140 semiconductor startups per year since 1990..ie 20 years(source :FSA ).On the average each startup has taken in between 35M$(low case)-90M$(High case)..and in some cases over 220M$( Icera Ltd..Bristol). Success rate has dropped to below 5%!
The most common denominator for lack of a successful result ,apart from product strategy/market errors, is a gross underestimation of costs/time to execute today's chip complexity, requiring far greater yet highly skilled microelectronics resources in both design and software and even more often in Design Verification and Validation .Typically entrepreneurial startup teams do not have the management /global operating skill sets to solve this problem by creation of a low cost design center offshore as most large multinationals and savvy US companies have done. As stated earlier the matter is often compounded by typical engineering management NIH and a strong resistance to work with remote design centers by engineers who have never worked with foreigners and who naturally prefer to have all team members on location.
